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+30 v/ 15 v operation 128 - position digital potentiometer ad7376 features 128 positions 10 k?, 50 k?, 100 k? 20 v to 30 v single - supply operation 10 v to 15 v dual - supply operation 3 - wire spi? - compatible serial interface thd 0.006% typical programmable preset power shutdown: less than 1 a i cmos? process technology ap plications high voltage dac programmable power supply programmable gain and offset adjustment programmable filters, delays actuator control audio volume control mechanical potentiometer replacement functional block dia gram v dd a w b v ss sdi clk cs sdo 7 7 r 7-bit la tch 7-bit seria l register q d ck ad7376 011 19-001 shdn shdn rs gnd figure 1. general description the ad7376 1 is one of the few high voltage, high performance digital potentiometers 2 on the market . this device can be used as a programmable resistor or resistor divider. the ad7376 performs the same electronic adjustment fun ction as mechanical potentiometers, variable resistors, and trimmers with enhanced resolution, solid - state reliability, and programmability. with digital rather than manual control, the ad7376 provides layout flexibility and allows close d - loop dynamic cont rollability. the ad7376 features sleep - mode programmability in shutdown that can be used to program the preset before device activation, thus providing an alternative to costly eeprom solutions. the ad7376 is available in 14 - lead tssop and 16 - lead wide bod y soic packages in 10 k?, 50 k?, and 100 k? options. all parts are guaranteed to operate over the ? 40c to +85c extended industrial temperature range. 1 patent number: 54952455. 2 the terms digital potentiometer and rdac are used interchangeab ly. rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third part ies that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respect ive owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 1997 C 2011 analog devices, inc. all rights reserved .
ad7376 rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagr am .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 10 k ? ve rsion ................................ 3 electrical characteristics 50 k ?, 100 k ? ve rsions ............... 4 timing specifications .................................................................. 5 3 - wire digital interface ................................................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 theory of opera tion ...................................................................... 12 programming the variable resistor ......................................... 12 programming the potentiometer divider ............................... 13 3 - wire serial bus digital interface .......................................... 13 daisy - chain operation ............................................................. 14 esd protection ........................................................................... 14 terminal voltage operating range ......................................... 14 power - up and power - down sequences .................................. 14 layout and powe r supply biasing ............................................ 15 applications information .............................................................. 16 high voltage dac ...................................................................... 16 programmable power supply ................................................... 16 audio volume control .............................................................. 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history 8 /11 rev. c to rev. d changes to output logic low conditions, table 1 ..................... 3 changes to output logic low conditions, table 2 ..................... 5 changes to figure 28 ...................................................................... 14 updates outline dimension s ........................................................ 18 7/09 rev. b to rev. c changes to features section ............................................................ 1 updates outline dimensions ........................................................ 19 changes to ordering guide .......................................................... 20 3 /07 rev. a to rev. b updated format .................................................................. universal changes to absolute maximum ratings ....................................... 7 changes to esd protection section ............................................. 14 changes to orderin g guide .......................................................... 19 11/05 rev. 0 to rev. a updated format .................................................................. universal deleted dip package .......................................................... universal changes to features ..........................................................................1 separated electrical characteristics into table 1 and table 2 .....3 separated interface timing into table 3 ........................................5 changes to table 1 through table 3 ...............................................3 a dded table 4 ....................................................................................6 added figure 2 ...................................................................................6 changes to absolute maximum ratings section ..........................7 deleted parametric test circuits section .......................................7 changes to typical performance characteristics ..........................9 added daisy - chain operation section ...................................... 14 added esd protection section ..................................................... 14 added terminal voltage operating range section ................... 14 added power - up and power - down sequences section ........... 14 added layout and power supply biasing section ..................... 15 added applications section .......................................................... 16 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 19 10/97 revision 0: initial versio n
ad7376 rev. d | page 3 of 20 specifications electrical character istics 10 k ? version v dd /v ss = 15 v 10%, v a = v dd , v b = v ss /0 v, ?40c < t a < +85c, unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheos tat mode resistor differential nonlinearity 2 r - dnl r wb , v a = nc, v dd /v ss = 15 v ?1 0.5 +1 lsb resistor nonlinearity 2 r - inl r wb , v a = nc, v dd /v ss = 15 v ?1 0.5 +1 lsb nominal resistor tolerance ?r ab t a = 25c ?30 +30 % resistance temperature coefficient 3 (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect ?300 ppm/c wiper resistance r w v dd /v ss = 15 v 120 200 ? v dd /v ss = 5 v 260 ? dc characteristics potentiometer divider mode integral nonlinear ity 4 inl v dd /v ss = 15 v ?1 0.5 +1 lsb differential nonlinearity 4 dnl v dd /v ss = 15 v ?1 0.5 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = 0x40 5 ppm/c full - scale error v wfse code = 0x7f, v dd /v ss = 15 v ?3 ?1.5 0 lsb zero - scale error v wzse code = 0x00, v dd /v ss = 15 v 0 1.5 3 lsb resistor terminals voltage range 5 v a, b, w v ss v dd v capacitance 6 a, b c a, b f = 1 mhz, measured to gnd, code = 0x40 45 pf capacitance 6 c w f = 1 mhz, measured to gnd, code = 0x40 60 pf shutdown supply current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.02 1 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 15 v 170 400 ? common - mode leakage i cm v a = v b = v w 1 na digital inputs and outputs input logic high v ih v dd = 5 v or 15 v 2.4 v input logic low v il v dd = 5 v or 15 v 0.8 v output logic high v oh r pull - u p = 2.2 k? to 5 v 4.9 v output logic low v ol i ol = 1.6 ma, v dd = 15 v 0.4 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd /v ss dual - supply range 4.5 16.5 v power supply range v dd single -s upply range, v ss = 0 4.5 33 v positive supply current i dd v ih = 5 v or v il = 0 v, v dd /v ss = 15 v 2 ma v ih = 5 v or v il = 0 v, v dd /v ss = 5 v 12 25 a negative supply current i ss v ih = 5 v or v il = 0 v, v dd /v ss = 15 v ?0.1 ma v ih = 5 v or v il = 0 v, v dd /v ss = 5 v ?0.1 ma power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd /v ss = 15 v 31.5 mw power supply rejection ratio psrr v dd /v ss = 15 v 10% ?0.2 0.05 +0.2 %/%
ad7376 rev. d | page 4 of 20 parameter symbol conditions min typ 1 max unit dynamic characteristics 6 , 9 , 10 bandwidth ?3 db bw code = 0x40 470 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.006 % v w settling time t s v a = 10 v, v b = 0 v, 1 lsb error band 4 s resistor noise voltage e n_wb r wb = 5 k?, f = 1 khz 0.9 nv hz 1 typical values represent average readings at 25 c, v dd = 15 v, and v ss = ? 15 v. 2 resistor posi tion nonlinearity error r - inl is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. r - dnl measures the relative step change from an ideal value measured between successive tap positions. parts are guarant eed monotonic. 3 pb - free parts have a 35 ppm/c temperature coefficient (tempco) . 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider , similar to a voltage output digital - to - analog converter . v a = v dd and v b = 0 v. dnl spe cification limits of 1 lsb maximum are g uaranteed m ono tonic operating conditions. 5 resistor t erminals a, b, and w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a t erminal. a terminal is open circuit in shutdown mode. 8 p diss is calculated from (i dd v dd ) + abs(i ss v ss ). cmos logic level inputs result in minimum power dissipation. 9 bandwidth, noise , and settling time s are dependent on the terminal resistance valu e chosen. the lowest r value results in the fastest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 10 all dynamic characteristics use v dd = 15 v and v ss = ? 15 v. electrical character istics 50 k ?, 100 k ? versions v dd /v ss = 15 v 10% or 5 v 10%, v a = v dd , v b = v ss /0 v, ?40c < t a < +85c, unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r - dnl r wb , v a = nc ?1 0.5 +1 lsb resistor nonlinearity 2 r - inl r wb , v a = nc, r ab = 50 k? ?1.5 0.5 +1.5 lsb r wb , v a = nc, r ab = 1 00 k? ?1 0.5 +1 lsb nominal resistor tolerance ?r ab t a = 25c ?30 +30 % resistance temperature coefficient 3 (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect ?300 ppm/c wiper resistance r w v dd /v ss = 15 v 120 200 ? v dd /v ss = 5 v 260 ? dc ch aracteristics potentiometer divider mode integral nonlinearity 4 inl ?1 0.5 +1 lsb differential nonlinearity 4 dnl ?1 0.5 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = 0x40 5 ppm/c full - scale error v wfse code = 0x7f ?2 ?0.5 0 lsb zero - scale error v wzse code = 0x00 0 0.5 1 lsb resistor terminals voltage range 5 v a, b, w v ss v dd v capacitance 6 a, b c a, b f = 1 mhz, measured to gnd, code = 0x40 45 pf capacitance 6 c w f = 1 mhz, measured to gnd, code = 0x40 60 pf shutdown supply current 7 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.02 1 a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = 15 v 170 400 ? common - mode leakage i cm v a = v b = v w 1 na
ad7376 rev. d | page 5 of 20 parameter symbol conditions min typ 1 max unit digital inputs and outputs input logic high v ih v dd = 5 v or 15 v 2.4 v input logic low v il v dd = 5 v or 15 v 0.8 v output logic high v oh r pull - u p = 2.2 k? to 5 v 4.9 v output logic low v ol i ol = 1.6 ma, v dd = 15 v 0.4 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd /v ss dual - supply range 4.5 16.5 v power supply range v dd si ngle - supply range, v ss = 0 4.5 33 v positive supply current i dd v ih = 5 v or v il = 0 v, v dd /v ss = 15 v 2 ma v ih = 5 v or v il = 0 v, v dd /v ss = 5 v 12 25 a negative supply current i ss v ih = 5 v or v il = 0 v, v dd /v ss = 15 v ?0.1 ma v ih = 5 v or v il = 0 v, v dd /v ss = 5 v ?0.1 ma power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd /v ss = 15 v 31.5 mw power supply rejection ratio psrr ?0.25 0.1 +0.25 %/% dynamic characteristics 6 , 9 , 10 bandwidth ?3 db bw r ab = 50 k?, code = 0x40 90 khz r ab = 100 k?, code = 0x40 50 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.002 % v w settling time t s v a = 10 v, v b = 0 v, 1 lsb error band 4 s resistor n oise voltage e n_wb r wb = 25 k?, f = 1 khz 2 nv hz 1 typical values represent average readings at 25 c, v dd = 15 v, and v ss = ? 15 v. 2 resistor position nonlinearity error r - inl is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. r - dnl measures the relative step change from an ideal valu e measured between successive tap positions. parts are guaranteed monotonic. 3 pb - free parts have a 35 ppm/c temperature coefficient. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider , similar to a voltage output digital - to - analog converter . v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are g uaranteed m ono tonic operating conditions. 5 resistor t erminals a, b, and w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. a terminal is open circuit in shutdown mode. 8 p diss is calculated from (i dd v dd ) + abs(i ss v ss ). cmos logic level inputs result in minimum power dissipation. 9 bandwidth, noise , and settli ng time s are dependent on the terminal resistance value chosen. the lowest r value results in the fastest settling time and highest bandwidth. the highest r value results in the minimum overall power consumption. 10 all dynamic characteristics use v dd = 15 v and v ss = ? 15 v. timing specification s table 3 . parameter symbol conditions min typ max unit interface timing characteristics 1 , 2 clock frequency f clk 4 mhz input clock pulse width t c h , t cl clock level high or low 120 ns data set up time t ds 30 ns data hold time t dh 20 ns clk to sdo propagation delay 3 t pd r pull - u p = 2.2 k?, c l < 20 pf 10 100 ns cs set up time t css 120 ns cs h igh pulse width t csw 150 ns reset pulse width t rs 120 ns clk fall to cs fall hold time t csh0 10 ns clk rise to cs rise hold time t csh 120 ns cs rise to clock rise setup t c s1 120 ns 1 guaranteed by design and not subject to production test. 2 see figure 3 for the location of the measured values. all input control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed fro m a voltage level of 1.6 v. switching characteristics are measured using v dd = 15 v and v ss = ?15 v . 3 propagation delay depends on value of v dd , r pull - u p , and c l .
ad7376 rev. d | page 6 of 20 3- wire digital interfa ce table 4. ad7376 serial data - word format 1 msb lsb d6 d5 d4 d3 d2 d1 d0 2 6 2 0 1 data is loaded msb first. d6 d5 d4 d3 d2 d1 d0 1 sdi 0 1 clk 0 1 cs 0 1 v out 0 011 19-002 rdac register load figure 2 . ad7376 3- wire digital interface timing diagram (v a = v dd , v b = 0 v, v w = v out ) 1 lsb error band 1 lsb t s t csw t csh t cl v dd v out 0v cs 0 1 t csh0 t css t ch 0 1 1 0 1 sdi (dat a in) sdo (dat a out) clk d x d x t ds t dh d' x d' x t pd_max t cs1 011 19-003 0 figu re 3 . detail timing diagram
ad7376 rev. d | page 7 of 20 absolute maximum rat ings t a = 25 c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +35 v v ss to gnd +0.3 v to ?16.5 v v dd to v ss ?0.3 v to +35 v v a , v b , v w to gnd v ss to v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 6 k?, a open, v dd /v ss = 30 v/0 v) 1 5 ma i wa continuous (r wa 6 k ? , b open, v dd /v ss = 30 v/0 v) 1 5 ma digital input and output voltages to gnd 0 v to v dd + 0.3 v operating temperature range ?40c to +85c maximum junction temperature (t jmax ) 2 150c storage temperature range ?65c to +150c reflow soldering peak temperature 2 60c time at peak temperature 20 sec to 40 sec package power dissipation (t jmax ? t a )/ ja thermal resistance ja 16- lead soic_w 120c/w 14- lead tssop 240c/w 1 maximum terminal current is bound by the maximum current handling of the switches, maximum p ower dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax C t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7376 rev. d | page 8 of 20 pin configur ations and function descriptions 011 19-004 a 1 b 2 v ss 3 gnd 4 w 14 nc 13 v dd 12 sdo 1 1 cs 5 rs 6 clk 7 shdn 10 sdi 9 nc 8 nc = no connect ad7376 t op view (not to scale) figure 4 . 14 - lead tssop pin configuration 011 19-005 a 1 b 2 v ss 3 gnd 4 w 16 nc 15 v dd 14 sdo 13 cs 5 shdn 12 rs 6 sdi 1 1 clk 7 nc 10 nc 8 nc 9 nc = no connect ad7376 t op view (not to scale) figure 5 . 16 - lead soic_w pin configuration table 6.pin function descriptions pin o. 14- lead tssp 16- lead sl nemon ic description 1 1 a a terminal. v ss v a v dd . 2 2 b b terminal. v ss v b v dd . 3 3 v ss negative power supply. 4 4 gnd digital ground. 5 5 cs chip select input, active low. when cs returns high, data is loaded into the wiper register. 6 6 rs reset to midscale. 7 7 clk serial clock input. positive edge triggered. 8 8, 9, 10 nc no connect. let it float or ground. 9 11 sdi serial data input (data loads msb first). 10 12 shdn shutdown. a terminal open ended; w and b terminals shorted. can be used as programmable preset. 1 11 13 sdo serial data output. 12 14 v dd positive power supply. 13 15 nc no connect. let it float or ground. 14 16 w wiper terminal. v s s v w v dd . 1 assert shutdown and pr ogram the device during power - up. then , deassert the shutdown to ach ieve the desirable preset level.
ad7376 rev. d | page 9 of 20 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.1 0.2 0.3 0.4 0.5 0 code (decimal) 0 128 16 32 48 64 80 96 1 12 v dd = +15v v ss = ?15v ?40c rheos ta t mode in l (lsb) +85c +25c 011 19-006 figure 6 . resistance step position nonlinearity error vs. code code (decimal) 0 128 16 32 48 64 80 96 1 12 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.1 0.2 0.3 0.4 0.5 0 rheos ta t mode dn l (lsb) v dd = +15v v ss = ?15v ?40c +85c +25c 011 19-007 figure 7 . relative resistance step change from ideal vs. code code (decimal) 0 128 16 32 48 64 80 96 1 12 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.1 0.2 0.3 0.4 0.5 0 potentiometer mode in l (lsb) v dd = +15v v ss = ?15v ?40c +85c +25c 011 19-008 figure 8 . potentiometer divider nonlinearity error vs. code code (decimal) 0 128 16 32 48 64 80 96 1 12 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0.1 0.2 0.3 0.4 0.5 0 potentiometer mode dn l (lsb) v dd = +15v v ss = ?15v ?40c +85c +25c 011 19-009 figure 9 . potentiometer divider differential nonlinearity error vs. code 20 ?4 ?40 011 19-010 temper a ture (c) supp l y current (a) 16 12 8 4 0 ?20 0 20 40 60 80 100 120 i dd @ v dd /v ss = 30v/0v i dd @ v dd /v ss = 15v i ss @ v dd /v ss = 30v/0v i ss @ v dd /v ss = 15v figure 10 . supply current (i dd , i ss ) vs. temperature 0.5 ?0.5 ?40 011 19-0 1 1 temper a ture (oc) shutdown current ( a) ?20 0 20 40 60 80 100 120 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 figure 11 . shutdown current vs. temperature
ad7376 rev. d | page 10 of 20 ?40 011 19-012 t ot al resis t ance, r ab (k) ?20 0 20 40 60 80 100 120 120 100 80 60 40 20 0 temper a ture (c) 10k 50k 100k v dd /v ss = 15v figure 12 . total resistance vs. temperature 350 0 ?40 011 19-013 temper a ture (c) wiper resis t ance r w ( ) ?20 0 20 40 60 80 100 120 300 250 200 150 100 50 r w @ v dd /v ss = 15v r w @ v dd /v ss = 5v figure 13 . wiper contact resistance vs. temperature 10k 50k 100k v dd /v ss = 15v 011 19-014 120 ?40 ?20 0 20 40 60 80 100 potentiometer mode tempco (ppm/c) code (decimal) 0 128 16 32 48 64 80 96 1 12 figure 14 . ( r wb /r wb )/ t rheostat mode tempco v dd /v ss = 15v 10k 50k 100k 011 19-015 code (decimal) 0 128 16 32 48 64 80 96 1 12 120 ?40 ?20 0 20 40 60 80 100 rheos ta t mode tempco (ppm/c) figure 15 . ( v wb /v wb )/ t potentiometer mode tempco 0 ?60 1k 1m 011 19-016 10k 100k ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 (db) (hz) 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 16 . 10 k? gain vs. frequency vs. code 0 ?60 1k 1m 011 19-017 10k 100k ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 (db) (hz) 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 17 . 50 k? gain vs. freq uency vs. code
ad7376 rev. d | page 11 of 20 0 ?60 1k 1m 01119-018 10k 100k ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 (db) (hz) 0x40 0x20 0x10 0x08 0x04 0x02 0x01 figure 18. 100 k gain vs. frequency vs. code 01119-019 ch1 5v ch2 5v m2s a ch1 4.20v 2 1 t 50% figure 19. midscale to midscale ? 1 transition glitch 80 0 100 1m 01119-020 frequency (hz) psrr (?db) 1k 10k 100k 60 40 20 code = 40 h , v a = v dd , v b = v ss ?psrr @ v dd /v ss = 15v dc 10% p-p ac +psrr @ v dd /v ss = 15v dc 10% p-p ac ?psrr @ v dd /v ss = 5v dc 10% p-p ac +psrr @ v dd /v ss = 5v dc 10% p-p ac figure 20. power supply rejection vs. frequency 0.1 0.0001 10 01119-021 frequency (hz) thd + n (%) 100k 100 1k 10k 0.001 0.01 10k ? 50k ? 100k ? v dd /v ss = 15v code = midscale v in = 1vrms figure 21. total harmonic distortion plus noise vs. frequency 1 0.001 0.001 01119-022 amplitude (v) thd + n (%) 10 0.01 0.1 1 0.01 0.1 v dd /v ss = 15v code = midscale f in = 1khz 10k ? 50k ? 100k ? figure 22. total harmonic distortion plus noise vs. amplitude 6 0 2 4 theoretic a l i wb_max (ma) code (decimal) 0128 16 32 48 64 80 96 112 01119-023 1 3 5 v dd /v ss = 30v/0v v a = v dd v b = 0v r ab = 50k ? r ab = 100k ? r ab = 10k ? figure 23. theoretical maximum current vs. code
ad7376 rev. d | page 12 of 20 theory of operation programming the variable resistor rheostat operation the part operates in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be left floating or tied to the w terminal as shown in figure 24. a w b a w b a w b 01119-024 figure 24. rheostat mode configuration the nominal resistance between terminals a and b, r ab , is available in 10 k, 50 k, and 100 k with 30% tolerance and has 128 tap points accessed by the wiper terminal. the 7-bit data in the rdac latch is decoded to select one of the 128 possible settings. figure 25 shows a simplified rdac structure. r s r s r s r s 0x01 0x7f 0x00 a w b sw b 01119-025 d6 d5 d4 d3 d2 d1 d0 rdac latch and decoder sw a r s = r nominal /128 shdn figure 25. ad7376 equivalent rdac circuit the general equation determining the digitally programmed output resistance between the w and the b terminals is w ab wb rr d dr ??? 128 )( (1) where: d is the decimal equivalent of the binary code loaded in the 7-bit rdac register from 0 to 127. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. the ad7376 wiper switches are designed with the transmission gate cmos topology, and the gate voltage is derived from the v dd . each switchs on resistance, r w , is a function of v dd and temperature (see figure 13). contrary to the temperature coefficient of r ab , the temperature coefficient of the wiper resistance is significantly higher because the wiper resistance doubles with every 100 increase. as a result, the user must take into consideration the contribution of r w on the desirable resistance. on the other hand, each switchs on resistance is insensitive to the tap point potential and remains relatively flat at 120 typical at a v dd of 15 v and a temperature of 25c. assuming that a 10 k part is used, the wipers first connection starts at the b terminal for programming code 0x00, where sw b is closed. the minimum resistance between terminals w and b is therefore 120 in general. the second connection is the first tap point, which corresponds to 198 ( r wb = 1/128 r ab + r w = 78 + 120 ) for programming code 0x01, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,042 ( r ab C 1 lsb + r w ). regardless of which settings the part is operating with, care should be taken to limit the current conducted between any a and b, w and a, or w and b terminals to a maximum dc current of 5 ma and a maximum pulse current of 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the w and a terminals also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded into the latch increases in value. the general equation for this operation is w ab wa rr d dr ?? ? ? 128 128 )( (2)
ad7376 rev. d | page 13 of 20 programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper w to terminal b and wiper w to terminal a that is proportional to the input voltage at terminal a to terminal b. unlike the polarity of v dd to gnd, which must be positive, voltage across terminal a to terminal b, wiper w to terminal a, and wiper w to terminal b can be at either polarity. a v i w b v o 011 19-026 figure 26 . potentiometer mode config uration if ignoring the effect of the wiper resistance for the purpose of approximation, connecting the terminal a to 30 v and the terminal b to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 1 lsb less than 30 v. each l sb of voltage is equal to the voltage applied across terminals a and b divided by the 128 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminals a and b is a w v d d v 128 ) ( = (3) a more accurate calculation that includes the effect of wiper resistance, v w , is b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = (4) operation of the digital potentiometer in the divider mode results in a more accurate operation over tempe rature. unlike when in rheostat mode, the output voltage in divider mode is primarily dependent on the ratio, not the absolute values, of the internal resistors r wa and r wb . therefore, the temperature drift reduces to 5 ppm/c. 3 - wire serial bus digi tal interface the ad7376 contains a 3 - wire digital interface ( cs , clk, and sdi). the 7 - bit serial word must be loaded msb first. the format of the word is shown in figure 2 . t he positive edge - sensitive clk inp ut requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. when cs is low , the clock loads data into the serial register upon each positive clock edge. the data set up and hold times in table 3 determine the valid timing requirements. the ad7376 uses a 7 - bit serial input data register word that is transferred to the internal rdac register when the cs line returns t o logic high. extra msb bits are ignored. the ad7376 powers up at a random setting. however, the midscale preset or any desirable preset can be achieved by manipulating rs or shdn with an extra i/o. when the r eset ( rs ) pin is asserted, the wiper resets to the midscale value. midscale reset can be achieved dynamically or during power - up if an extra i/o is used. when the shdn pin is asserted, the ad7376 opens sw a to l et the terminal a float and to short wiper w to terminal b. the ad7376 consumes negligible power during the shutdown mode and resumes the previous setting once the shdn pin is released. on the other hand, the ad7376 can be programmed with any settings during shutdown. with an extra programmable i/o asserting shutdown during power - up, this unique feature allows the ad7376 with programmable preset at any desirable level. table 7 shows the logic truth table for all operation s. table 7. i nput logic control truth table 1 clk cs rs shdn register activity l l h h enables sr, enables sdo pin. p l h h shifts one bit in from the sdi pin. the seventh previously entered bit is s hifted out of the sdo pin. x p h h loads sr data into 7 - bit rdac latch. x h h h no operation. x x l h sets 7 - bit rdac latch to midscale, wiper centered, and sdo latch cleared. x h p h latches 7 - bit rdac latch to 0x40. x h h l opens circuits resistor o f terminal a, connects wiper w to terminal b, turns off sdo output transistor. 1 p = positive edge, x = dont care, and sr = shift register.
ad7376 rev. d | page 14 of 20 daisy - chain operation 011 19-027 cs sdi seria l register d ck q rs shdn sdo rs clk figure 27 . detail ed sdo output schematic of the ad7376 figure 27 shows the details of the serial data output pin (sdo). sdo shifts out the sdi content in the previous frame; therefore, it can be used for daisy - chaining multiple devices. the sdo pin contains an open - drain n - channel mosfet and requires a pull - up resistor if the sdo function is used. us ers need to tie the sdo pin of one package to the sdi pin of the next package. for example, in figure 28, if two ad7376s are daisy - chained, a total of 14 bits of data are required for each operation. the first set of seven bits goes to u2; the second set of seven bits goes to u1. cs should be kept low until all 14 bits are clocked into their respective serial registers. then cs is pulled high to complete the operation. when daisy - cha ining multiple devices, users may need to increase the clock period because the pull - up resistor and th e capacitive loading at the sdo to sdi interface may induce a time delay to subsequent devices. ad7376 sdo sdi clk cs ad7376 sdo sdi clk cs c 5v r pu 2.2k mosi ss sclk 011 19-028 u1 u2 figure 28 . daisy - chain configu ration esd protection all digital inputs are protected with a s eries input resistor and an esd structure shown in figure 29 . these structures apply to digital input pins cs , clk, sdi , rs , and shdn . input 340 logic pins v dd gnd 011 19-029 figure 29 . equivalent esd protection circuit all analog termi nals are also protected by esd protection diodes, as shown in figure 30. v ss v dd a w b 011 19-030 figure 30 . equivalent esd protection analog pins terminal voltage ope rating range the ad7376 v dd and v ss power supplies define the boundary conditions for proper 3 - terminal digital potentiometer oper - ation. applied signals present on terminals a, b, and w that are more positive than v dd or more negative than v ss will be clamped by the internal forward - biased diodes (see figure 30). power - up and power - down sequences because of the esd protection diodes that limit the voltage comp liance at terminals a, b, and w (see figure 30 ), it is important to power v dd /v ss before applying voltage to terminals a, b, and w. otherwise, the diodes are forward biased such that v dd /v ss are powered unintentionally and affec t the system. similarly, v dd /v ss should be powered down last. the ideal power - up sequence is in the following order: gnd, v dd , v ss , digital inputs, and v a /v b /v w . the order of powering v a , v b , v w , and the digital inputs is not important, as long as they are powered after v dd /v ss .
ad7376 rev. d | page 15 of 20 layout and power supply biasing it is a good practice to employ a compact, minimum lead-length layout design. the leads to the input should be as direct as possible, with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors. low esr (equivalent series resistance) 1 f to 10 f tantalum or electrolytic capacitors should be applied at the supplies to minimize transient disturbances and filter low frequency ripple. figure 31 illustrates the basic supply bypassing configuration for the ad7376. the ground pin of the ad7376 is a digital ground reference. to minimize the digital ground bounce, the ad7376 digital ground terminal should be joined remotely to the analog ground (see figure 31). v dd v dd v ss v ss gnd c3 ad7376 c4 c1 + + c2 10f 10f 0.1f 0.1f 01119-031 figure 31. power supply bypassing
ad7376 rev. d | page 16 of 20 applications information high voltage dac the ad7376 can be configured as a high voltage dac as high as 30 v. the circuit is shown in figure 32. the output is ? ? ? ? ? ? ? ? ? ? ? ? ?? ? 1 2 1v2.1 128 )( r r d dv o (5) where d is the decimal code from 0 to 127. ad7376 u2 ad8512 v+ v? ad8512 v out v dd u1b v dd r bias adr512 d1 r2 r1 b 100k ? 0 1119-032 u1a figure 32. high voltage dac programmable power supply with a boost regulator such as adp1611, ad7376 can be used as the variable resistor at the regulators fb pin to provide the programmable power supply (see figure 33). the output is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? 2 128 1v23.1 r r d v ab o (6) note that the ad7376s v dd is derived from the output. initially l1 acts as a short, and v dd is one diode voltage drop below +5 v. the output slowly establishes to the final value. the ad7376 shutdown sleep-mode programming can be used to program a desirable preset level at power-up. ad7376 adp1611 1.23v c c 150pf r c 220k ? c out 10f v out d1 l1 4.7f in gnd ss fb rt sw comp u2 c1 0.1f v dd r1 100k ? a w b c in 10f 5v r2 8.5k ? c ss 22nf 01119-033 u1 sd figure 33. programmable power supply
ad7376 rev. d | page 17 of 20 audio volume control because of its good thd performance and high voltage capability, the ad7376 can be used for digital volume control. if ad7376 is used dire ctly as an audio attenuator or gain amplifier, a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. to prevent this, a zero - crossing window detector can be i nserted to the cs line to delay the device update until the audio signal crosses the window. since the input signal can operate on top of any dc levels rather than absolute zero volt level, zero - crossing , in this case , means the sign al is ac - coupled and the dc offset level is the signal zero reference point. the configuration to reduce zipper noise and the result of using this configuration are shown in figure 35 and figure 34, respectively. the input is ac - coupled by c1 and attenuated down before feeding into the window comparator formed by u 2 , u 3 , and u 4b . u 6 is used to establish the signal zero reference. the upper limit of the comparator is set above its offset and, therefore , the output pulses high whenever the input falls between 2.502 v and 2.497 v (or 0.005 v window) in this example. this output is anded with the chip select signal such that the ad7376 updates whenever the signal crosses the window. to avoid constant upda te of the device, the chip select signal should be programmed as two pulses, rather than the one shown in figure 2 . in figure 34 , the lower trace shows that the volume level changes from a quarter sc ale to full scale when a signal change occurs near the zero - crossing window. the ad7376 shutdown sleep - mode programming feature can be u sed to mute the device at power - up by holding shdn low and programming zero scale. 011 19-035 channe l 1 freq = 20.25khz 1.03v p-p 1 2 notes 1. the lower trace shows th a t the volume leve l changes from quarter scale t o ful l scale, with the change occurring near the zero-crossing windo w . figure 34 . input (trace 1) and output (trace 2) of the circuit in figure 35 v dd v ss cs clk sdi v+ v? ad7376 100k +15v ?15v c3 0.1f c2 0.1f a b w gnd sdi clk u1 +15v ?15v v out u5 011 19-034 cs v+ v+ v? v? adcm371 adcm371 +5v +5v u3 u2 r1 100k r2 200 +5v v in u4 a u4b 1 6 2 4 5 7408 7408 v+ v? ad8541 +5v u6 r3 100 r4 90k r5 10k c1 1f figure 35 . audio volume control with zipper noise reduction
ad7376 rev. d | page 18 of 20 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 sea ting plane figure 36 . 14 - lead thin shrink small outline package [tssop] (ru - 14) dimensions shown in millimeters controlling dimensions are in millimeter s; inch dimensions (in p arenthese s) are rounded-off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.01 18) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500 ) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) sea ting plane 8 0 1 6 9 8 1 1.27 (0.0500) bsc 03 -2 7-20 07-b figure 37 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimensions shown in millimeters and (inches)
ad7376 rev. d | page 19 of 20 o rdering guide model 1 k? temperature range package description 2 , 3 package option ordering quantity AD7376ARUZ10 10 ?40c to +85c 14- lead tssop ru -14 96 AD7376ARUZ10 -r7 10 ?40c to +85c 14- lead tssop ru -14 1,000 ad7376arwz10 10 ?40c to +85c 16- lead soic_w rw -16 47 ad737 6arwz10 -rl 10 ?40c to +85c 16- lead soic_w rw -16 1,000 ad7376aru z 50- reel7 50 ?40c to +85c 14- lead tssop ru -14 1,000 ad7376aruz50 50 ?40c to +85c 14- lead tssop ru -14 96 ad7376arwz50 50 ?40c to +85c 16- lead soic_w rw -16 47 AD7376ARUZ100 100 ?40c to +85c 14- lead tssop ru -14 96 AD7376ARUZ100 - r7 100 ?40c to +85c 14- lead tssop ru -14 1,000 ad7376arwz100 100 ?40c to +85c 16- lead soic_w rw -16 47 eval - ad7376ebz 10 1 1 z = rohs compliant part . 2 i n soic rw - 16 package top marking: line 1 shows ad7376; line 2 shows the branding information, where a10 = 10 k ? , a 50 = 50 k ? , and a100 = 100 k ? ; line 3 shows a # top marking with the date code in yyww; and line 4 shows the lot number. 3 in tssop - 14 package top marking: line 1 shows 7376; line 2 shows the branding information, where a10 = 10 k ? , a 50 = 50 k ? , and a100 = 100 k ? ; line 3 shows a # top marking with the date code in yww; back side shows the lot number.
ad7376 rev. d | page 20 of 20 notes ? 1997 C 2011 analog devices, inc. al l rights reserved. trademarks and registered trademarks are the property of their respective owners. d01119 - 0- 8/11(d)

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